(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to the formation of shallow trench isolation structures in integrated circuit devices.
(2) Description of the Prior Art
Shallow trench isolation (STI) is a commonly used technique for forming electrical isolation structures in integrated circuit manufacture. STI structures are smaller than the traditional local oxidation of silicon (LOCOS) and are therefore better suited for modern ULSI circuits.
The formation of the shallow trench is the most important part of the STI process. Specifically, it is important that the STI trenches be formed at a consistent depth across the integrated circuit wafer and from device to device.
Achieving uniform process capability for the STI structures is especially difficult at CMOS process technologies of less than 0.25 microns. This is because different devices may exhibit very different densities of STI structures. This effect is called reticle transmission (RT). Reticle transmission is simply the open area in the reticle divided by the closed area expressed in percentage. RT describes the percentage of light that will be transmitted through the reticle.
If the RT percentage is very different between two devices, the silicon etching rate of the reactive ion etching (RIE) process will also be different for these devices. In such circumstances, either the trench etch process must be specifically tuned for each device or the process specifications must be unduly large.
Referring to FIG. 1, a cross-section of a partially completed prior art STI structure is shown. A trench has been etched in a silicon substrate 10. Overlying the substrate 10 are a pad oxide layer 14 and a silicon nitride hard mask layer 18. A RIE etch has been performed to create the trench using the hard mask layer 18 as a mask. Note that the aspect ratio of the overall trench is defined by the depth L3 divided by the width L2. Note additionally that the depth of the trench etched into the silicon substrate 10 is L1.
It should be clear that, as the trench is etched into the substrate 10, the aspect ratio is increasing. In RIE etching, as the aspect ratio increases, the etch rate will be changed due to microloading effects. This makes controlling the final trench depth L1 more difficult, especially since there is no etch endpoint detection mechanism. In addition, the etch rate is also affected by factors such as RT and the cleanliness of the etch chamber. Consequently, the final depth L1 for a given STI structure can vary greatly from device to device and from production lot to production lot. Finally, because silicon nitride 18 is used as a hard mask for the etch, some nitrogen is released into the chamber. This nitrogen is deposited in the polymer film that forms on the inside surfaces of the trench during the etch. Removal of the polymer film during the subsequent cleaning operation is made difficult by the presence of this nitrogen inclusion.
Several prior art approaches attempt to improve the manufacturing method for forming trenches in the silicon substrate. U.S. Pat. No. 5,814,547 to Chang teaches a process for dry etching both shallow and deep trenches simultaneously. A hard mask of silicon dioxide over a layer of silicon nitride over a layer of silicon dioxide is used. U.S. Pat. No. 5,776,808 to Muller et al discloses a process to form trenches for capacitors where a TEOS layer is used as the hard mask for the etch. The TEOS is then etched away using an underlying polysilicon layer as an etching stop. U.S. Pat. No. 5,696,021 to Chan et al teaches a process to form isolation structures with side trenches. A layer of Si.sub.3 N.sub.4 over a polysilicon layer is used as a hard mask for the trench etch.